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preliminary notebook pc system frequency generator for k6 processors W215B cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 document #: 38-07222 rev. *a* revised december 15, 2002 features ? generates system clocks for cpu, ioapic, sdram, pci, usb plus 14.318 mhz (ref0:1) mode input pin selects optional power management input control pins (reconfigures pins 26 and 27) two fixed outputs separately selectable as 24-mhz or 48-mhz (default = 48-mhz) v ddq3 = 3.3v5%, v ddq2 = 3.3v5% uses external 14.318-mhz crystal available in 48-pin tssop (6.1-mm) 10 ? cpu output impedance table 1. pin selectable frequency 95/100_sel cpu, sdram clocks (mhz) pci clocks 095.0cpu/3 1 100.0 cpu/3 pin configuration block diagram vddq3 ref0 vddq2 ioapic cpu0 cpu1 cpu2 cpu3 sdram0 sdram1 sdram2 sdram3 sdram4 sdram5 sdram6/cpustop# sdram7/pcistop# pci_f pci0 xtal pll ref freq pll 1 95/100_sel mode x2 x1 ref1 vddq3 stop output control stop output control pci1 pwr_dwn# power down control pci2 pci3 pci4 pci5 48/24mhz 48/24mhz pll2 osc i/o control vddq2 ref1 ref0 gnd x1 x2 mode vddq3 pci_f pci0 gnd pci1 pci2 pci3 pci4 vddq3 pci5 gnd 95/100_sel reserved reserved vddq3 48/24mhz 48/24mhz gnd W215B vddq3 cpu_2.5# vddq2 ioapic pwr_dwn# gnd cpu0 cpu1 vddq2 cpu2 cpu3 gnd sdram0 sdram1 vddq3 sdram2 sdram3 gnd sdram4 sdram5 vddq3 sdram6/cpu_stop# sdram7/pci_stop# vddq3 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 cpu_2.5#
W215B preliminary document #: 38-07222 rev. *a* page 2 of 14 pin definitions pin name pin no. pin type pin description cpu0:3 42, 41, 39, 38 o cpu outputs 0 through 3: these four cpu outputs are controlled by the cpu_stop# control pin. output voltage swing is controlled by voltage applied to vddq2. pci0:5 9, 11, 12, 13, 14, 16 o pci bus outputs 0 through 5: these six pci outputs are controlled by the pci_stop# control pin. output voltage swing is controlled by voltage applied to vddq3. pci_f 8 o free running pci output: unlike pci0:5 outputs, this output is not controlled by the pci_stop# control pin. output voltage swing is controlled by voltage applied to vddq3. sdram0:5 36, 35, 33, 32, 30, 29 o sdram clock outputs 0 through 5: these six sdram clock outputs run synchro- nous to the cpu clock outputs. output voltage swing is controlled by voltage applied to vddq3. sdram6/ cpu_stop# 27 i/o sdram clock output 6 or cpu clock output stop control: this pin has dual functions, selectable by the mode input pin. when mode = 0, this pin becomes the cpu_stop# input. when mode = 1, this pin becomes sdram clock output 6. regarding use as a cpu_stop# input: when brought low, clock outputs cpu0:3 are stopped low after completing a full clock cycle (2 ? 3 cpu clock latency). when brought high, clock outputs cpu0:3 are started beginning with a full clock cycle (2 ? 3 cpu clock latency). regarding use as a sdram clock: output voltage swing is controlled by voltage applied to vddq3. sdram7/ pci_stop# 26 i/o sdram clock output 7 or pci clock output stop control: this pin has dual functions, selectable by the mode input pin. when mode = 0, this pin becomes the pci_stop# input. when mode = 1, this pin becomes sdram clock output 7. pci_stop# input: when brought low, clock outputs pci0:5 are stopped low after completing a full clock cycle. when brought high, clock outputs pci0:5 are started beginning with a full clock cycle. clock latency provides one pci_f rising edge of pci clock following pci_stop# state change. regarding use as a sdram clock: output voltage swing is controlled by voltage applied to vddq3. ioapic 45 o i/o apic clock output: provides 14.318-mhz fixed frequency. the output voltage swing is controlled by vddq2. 48/24mhz 22, 23 o 48-mhz / 24-mhz output: fixed clock outputs that default to 48 mhz following device power-up. either or both can be changed to 24 mhz through use of the serial data interface (byte 0, bits 2 and 3). output voltage swing is controlled by voltage applied to vddq3 ref0:1 2, 1 o fixed 14.318-mhz outputs 0 through 1: used for various system applications. out- put voltage swing is controlled by voltage applied to vddq3. ref0 is stronger than ref1 and should be used for driving isa slots. cpu_2.5# 47 i set to logic 1 for 3.3v cpu i/o. 95/100_sel 18 i 95- or 100-mhz input selection: selects power-up default cpu clock frequency as shown in table 1 on page 1 (also determines sdram and pci clock frequency selec- tions). x1 4 i crystal connection or external reference frequency input: this pin has dual functions. it can be used as an external 14.318-mhz crystal connection or as an external reference frequency input. x2 5 i crystal connection: an input connection for an external 14.318-mhz crystal. if using an external reference, this pin must be left unconnected.
W215B preliminary document #: 38-07222 rev. *a* page 3 of 14 pwr_dwn# 44 i power-down control: when this input is low, device goes into a low-power standby condition. all outputs are actively held low while in power-down. cpu, sdram, and pci clock outputs are stopped low after completing a full clock cycle (2 ? 4 cpu clock cycle latency). when brought high, cpu, sdram, and pci outputs start with a full clock cycle at full operating frequency (3 ms maximum latency). mode 6 i mode control: this input selects the function of device pin 26 (sdram7/pci_stop#) and pin 27 (sdram6/cpu_stop#). refer to description for those pins. vddq3 7, 15, 21, 25 28, 34, 48 p power connection: power supply for pci0:5, ref0:1, and 48-/24-mhz output buff- ers. connected to 3.3v supply. vddq2 46, 40 p power connection: power supply for ioapic0, cpu0:3 output buffer. connected to 3.3v supply. gnd 3, 10, 17, 24, 31, 37, 43 g ground connection: connect all ground pins to the common system ground plane. reserved 19, 20 i reserved pins: connect to logic 1. pin definitions pin name pin no. pin type pin description
W215B preliminary document #: 38-07222 rev. *a* page 4 of 14 absolute maximum ratings [1] stresses greater than those listed in this table may cause per- manent damage to the device. these represent a stress rating only. operation of the device at these or any other conditions above those specified in the operating sections of this specifi- cation is not implied. maximum conditions for extended peri- ods may affect reliability. parameter description rating unit v dd , v in voltage on any pin with respect to gnd ? 0.5 to +7.0 v t stg storage temperature ? 65 to +150 c t b ambient temperature under bias ? 55 to +125 c t a operating temperature 0 to +70 c esd prot input esd protection 2 (min.) kv dc electrical characteristics t a = 0 c to +70 c, v ddq3 = 3.3v5% (3.135 ? 3.465v), f xtl = 14.31818 mhz, v ddq2 = 3.3v5% parameter description test condition min. typ. max. unit supply current i ddq3 supply current (3.3v) cpu0:3 = 100 mhz outputs loaded [2] 150 ma i ddq2 supply current (3.3v) cpu0:3 = 100 mhz outputs loaded [2] 80 ma logic inputs v il input low voltage 0.8 v v ih input high voltage 2.0 v i il input low current [3] 10 a i ih input high current [3] 10 a clock outputs v ol output low voltage i ol = 2 ma 50 mv v oh output high voltage i oh = ? 1 ma 3.1 v i ol output low current cpu0:3 v ol = 1.5v 140 ma sdram0:7 v ol = 1.5v 110 ma pci_f, pci0:5 v ol = 1.5v 110 ma ioapic v ol = 1.5v 95 ma ref0 v ol = 1.5v 75 ma ref1 v ol = 1.5v 70 ma 48/24mhz v ol = 1.5v 70 ma i oh output high current cpu0:3 v ol = 1.5v 120 ma sdram0:7 v ol = 1.5v 95 ma pci_f, pci0:5 v ol = 1.5v 95 ma ioapic v ol = 1.5v 95 ma ref0 v ol = 1.5v 80 ma ref1 v ol = 1.5v 62 ma 48/24mhz v ol = 1.5v 60 ma notes: 1. multiple supplies: the voltage on any input or i/o pin cannot exceed the power pin during power-up. power supply sequencing i s not required. 2. all clock outputs loaded with maximum lump capacitance test load specified in ac electrical characteristics section. 3. W215B logic inputs have internal pull-up devices (not cmos level).
W215B preliminary document #: 38-07222 rev. *a* page 5 of 14 ac electrical characteristics (lump load model) t a = 0 c to +70 c, v ddq3 = 3.3v5% (3.135 ? 3.465v) f xtl = 14.31818 mhz, v ddq2 = 3.3v5% ac clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the clock output. crystal oscillator v th x1 input threshold voltage [4] v ddq3 = 3.3v 1.65 v c load load capacitance, imposed on external crystal [5] 14 pf c in,x1 x1 input capacitance [6] pin x2 unconnected 28 pf pin capacitance/inductance c in input pin capacitance except x1 and x2 5 pf c out output pin capacitance 6pf l in input pin inductance 7nh notes: 4. x1 input threshold voltage (typical) is v ddq3 /2. 5. the W215B contains an internal crystal load capacitor between pin x1 and ground and another between pin x2 and ground. total load placed on crystal is 14 pf; this includes typical stray capacitance of short pcb traces to crystal. 6. x1 input capacitance is applicable when driving x1 with an external clock source (x2 is left unconnected). dc electrical characteristics (continued) t a = 0 c to +70 c, v ddq3 = 3.3v5% (3.135 ? 3.465v), f xtl = 14.31818 mhz, v ddq2 = 3.3v5% parameter description test condition min. typ. max. unit ftg test point *20pf for cpu, ref1, ioapic, 24mhz & 48mhz *30pf for sdram & pci cpu clock outputs, cpu0:3 (lump capacitance test load = 20 pf) parameter description test condition/comments cpu = 100 mhz unit min. typ. max. t p period measured on rising edge at 1.5v 10 ns f frequency, actual determined by pll divider ratio 100 mhz t h high time duration of clock cycle above 2.4v 5 ns t l low time duration of clock cycle below 0.4v 5 ns t r output rise edge rate measured from 0.4v to 2.4v 1 4 v/ns t f output fall edge rate measured from 2.4v to 0.4v 1 4 v/ns t d duty cycle measured on rising and falling edge at 1.5v 45 50 55 % t jc jitter, cycle-to-cycle measured on rising edge at 1.5v. maximum differ- ence of cycle time between two adjacent cycles. 500 ps t sk output skew measured on rising edge at 1.5v 250 ps f st frequency stabilization from power-up (cold start) assumes full supply voltage reached within 1 ms from power-up. short cycles exist prior to frequency stabilization. 3ms z o ac output impedance average value during switching transition. used for determining series termination value. 10
W215B preliminary document #: 38-07222 rev. *a* page 6 of 14 sdram clock outputs, sdram0:7 (lump capacitance test load = 30 pf) parameter description test condition/comments cpu = 100 mhz unit min. typ. max. t p period measured on rising edge at 1.5v 10 ns f frequency, actual determined by pll divider ratio 100 mhz t r output rise edge rate measured from 0.4v to 2.4v 1 4 v/ns t f output fall edge rate measured from 2.4v to 0.4v 1 4 v/ns t d duty cycle measured on rising and falling edge at 1.5v 45 50 55 % t jc jitter, cycle-to-cycle measured on rising edge at 1.5v. maximum differ- ence of cycle time between two adjacent cycles. 500 ps t sk output skew measured on rising edge at 1.5v 100 ps t sk cpu to sdram clock skew covers all cpu/sdram outputs. measured on rising edge at 1.5v. 1.5 ns f st frequency stabilization from power-up (cold start) assumes full supply voltage reached within 1 ms from power-up. short cycles exist prior to frequency stabilization. 3ms z o ac output impedance average value during switching transition. used for determining series termination value. 16 ? pci clock outputs, pci0:5 (lump capacitance test load = 30 pf) parameter description test condition/comments cpu = 100 mhz unit min. typ. max. t p period measured on rising edge at 1.5v 30 ns f frequency, actual determined by pll divider ratio 33.3 mhz t h high time duration of clock cycle above 2.4v 12 ns t l low time duration of clock cycle below 0.4v 12 ns t r output rise edge rate 1 4 v/ns t f output fall edge rate 1 4 v/ns t d duty cycle measured on rising and falling edge at 1.5v 45 50 55 % t jc jitter, cycle-to-cycle measured on rising edge at 1.5v. maximum difference of cycle time between two adjacent cycles. 500 ps t sk output skew measured on rising edge at 1.5v 250 ps t o cpu to pci clock skew covers all cpu/pci outputs. measured on rising edge at 1.5v. cpu leads pci output. 14ns f st frequency stabilization from power-up (cold start) assumes full supply voltage reached within 1 ms from power-up. short cycles exist prior to frequency stabilization. 3ms z o ac output impedance average value during switching transition. used for determining series termination value. 15 ?
W215B preliminary document #: 38-07222 rev. *a* page 7 of 14 i/o apic clock output (lump capacitance test load = 20 pf) parameter description test condition/comments cpu = 100 mhz unit min. typ. max. f frequency, actual frequency generated by crystal oscillator 14.31818 mhz t r output rise edge rate 1 4 v/ns t f output fall edge rate 1 4 v/ns t d duty cycle measured on rising and falling edge at 1.5v 45 50 55 % f st frequency stabilization from power-up (cold start) assumes full supply voltage reached within 1 ms from power-up. short cycles exist prior to frequency stabilization. 1.5 ms z o ac output impedance average value during switching transition. used for determining series termination value. 15 ? ref0 clock output (lump capacitance test load = 45 pf) parameter description test condition/comments cpu = 100 mhz unit min. typ. max. f frequency, actual frequency generated by crystal oscillator 14.318 mhz t r output rise edge rate 1 4 v/ns t f output fall edge rate 1 4 v/ns t d duty cycle measured on rising and falling edge at 1.5v 45 50 55 % f st frequency stabilization from power-up (cold start) assumes full supply voltage reached within 1 ms from power-up. short cycles exist prior to frequency stabilization. 1.5 ms z o ac output impedance average value during switching transition. used for determining series termination value. 16 ? ref1 clock output (lump capacitance test load = 20 pf) parameter description test condition/comments cpu = 100 mhz unit min. typ. max. f frequency, actual frequency generated by crystal oscillator 14.318 mhz t r output rise edge rate 0.5 2 v/ns t f output fall edge rate 0.5 2 v/ns t d duty cycle measured on rising and falling edge at 1.5v 45 55 % f st frequency stabilization from power-up (cold start) assumes full supply voltage reached within 1 ms from power-up. short cycles exist prior to frequency stabilization. 1.5 ms z o ac output impedance average value during switching transition. used for determining series termination value. 25 ?
W215B preliminary document #: 38-07222 rev. *a* page 8 of 14 ac electrical characteristics (transmission line model) t a = 0 c to +70 c, v ddq3 = 3.3v5% (3.135 ? 3.465v), f xtl = 14.31818 mhz, v ddq2 = 3.35% ac clock parameters are tested and guaranteed over stated operating conditions using the stated transmission line load at the clock output. 48-/24-mhz clock output (lump capacitance test load = 20 pf) parameter description test condition/comments cpu = 100 mhz unit min. typ. max. m/n pll ratio 57/17 t r output rise edge rate 0.5 2 v/ns t f output fall edge rate 0.5 2 v/ns t d duty cycle measured on rising and falling edge at 1.5v 45 50 55 % f st frequency stabilization from power-up (cold start) assumes full supply voltage reached within 1 ms from power-up. short cycles exist prior to fre- quency stabilization. 3ms z o ac output impedance average value during switching transition. used for determining series termination value. 25 ? ftg 6 inches 60 ohm trace 22 ohm cpu clock outputs, cpu0:3 (test load: r = 33 ? ; c = 22 pf) parameter description test condition/comments cpu = 100 mhz unit min. typ. max. t p period measured on rising edge at 1.5v 10 ns f frequency, actual determined by pll divider ratio 100 mhz t h high time duration of clock cycle above 2.4v 5 ns t l low time duration of clock cycle below 0.4v 5 ns t r output rise edge rate measured from 0.4v to 2.4v 1 4 v/ns t f output fall edge rate measured from 2.4v to 0.4v 1 4 v/ns t d duty cycle measured on rising and falling edge at 1.5v 45 50 55 % t jc jitter, cycle-to-cycle measured on rising edge at 1.5v. maximum differ- ence of cycle time between two adjacent cycles. 250 ps t sk output skew measured on rising edge at 1.5v 250 ps f st frequency stabilization from power-up (cold start) assumes full supply voltage reached within 1 ms from power-up. short cycles exist prior to frequency stabilization. 3ms z o ac output impedance average value during switching transition. used for determining series termination value. 10 ?
W215B preliminary document #: 38-07222 rev. *a* page 9 of 14 sdram clock outputs, sdram0:7 (test load: r = 22 ? ; c = 22 pf) parameter description test condition/comments cpu = 100 mhz unit min. typ. max. t p period measured on rising edge at 1.5v 10 ns f frequency, actual determined by pll divider ratio 100 mhz t r output rise edge rate measured from 0.4v to 2.4v 1 4 v/ns t f output fall edge rate measured from 2.4v to 0.4v 1 4 v/ns t d duty cycle measured on rising and falling edge at 1.5v 45 50 55 % t jc jitter, cycle-to-cycle measured on rising edge at 1.5v. maximum differ- ence of cycle time between two adjacent cycles. 250 ps t sk output skew measured on rising edge at 1.5v 100 ps t sk cpu to sdram clock skew covers all cpu/sdram outputs. measured on rising edge at 1.5v. 850 ps f st frequency stabilization from power-up (cold start) assumes full supply voltage reached within 1 ms from power-up. short cycles exist prior to frequency stabilization. 3ms z o ac output impedance average value during switching transition. used for determining series termination value. 16 ? pci clock outputs, pci0:5 (test load: r = 22 ? ; c = 22 pf) parameter description test condition/comments cpu = 100 mhz unit min. typ. max. t p period measured on rising edge at 1.5v 30 ns f frequency, actual determined by pll divider ratio 33.3 mhz t h high time duration of clock cycle above 2.4v 12 ns t l low time duration of clock cycle below 0.4v 12 ns t r output rise edge rate 1 4 v/ns t f output fall edge rate 1 4 v/ns t d duty cycle measured on rising and falling edge at 1.5v 45 50 55 % t jc jitter, cycle-to-cycle measured on rising edge at 1.5v. maximum difference of cycle time between two adjacent cycles. 250 ps t sk output skew measured on rising edge at 1.5v 250 ps t o cpu to pci clock skew covers all cpu/pci outputs. measured on rising edge at 1.5v. cpu leads pci output. 14ns f st frequency stabilization from power-up (cold start) assumes full supply voltage reached within 1 ms from power-up. short cycles exist prior to frequency stabilization. 3ms z o ac output impedance average value during switching transition. used for determining series termination value. 15 ?
W215B preliminary document #: 38-07222 rev. *a* page 10 of 14 i/o apic clock output (test load: r = 33 ? ; c = 22 pf) parameter description test condition/comments cpu = 100 mhz unit min. typ. max. f frequency, actual frequency generated by crystal oscillator 14.31818 mhz t r output rise edge rate 1 4 v/ns t f output fall edge rate 1 4 v/ns t d duty cycle measured on rising and falling edge at 1.5v 45 50 55 % f st frequency stabilization from power-up (cold start) assumes full supply voltage reached within 1 ms from power-up. short cycles exist prior to frequency stabilization. 1.5 ms z o ac output impedance average value during switching transition. used for determining series termination value. 15 ? ref0 clock output (test load: r = 33 ? ; c = 22 pf) parameter description test condition/comments cpu = 100 mhz unit min. typ. max. f frequency, actual frequency generated by crystal oscillator 14.318 mhz t r output rise edge rate measured from 0.4v to 2.4v 1 4 v/ns t f output fall edge rate measured from 2.4v to 0.4v 1 4 v/ns t d duty cycle measured on rising and falling edge at 1.5v 45 50 55 % f st frequency stabilization from power-up (cold start) assumes full supply voltage reached within 1 ms from power-up. short cycles exist prior to frequency stabilization. 1.5 ms z o ac output impedance average value during switching transition. used for determining series termination value. 16 ? ref1 clock output (lump capacitance test load = 20 pf) parameter description test condition/comments cpu = 100 mhz unit min. typ. max. f frequency, actual frequency generated by crystal oscillator 14.318 mhz t r output rise edge rate 0.5 2 v/ns t f output fall edge rate 0.5 2 v/ns t d duty cycle measured on rising and falling edge at 1.5v 45 55 % f st frequency stabilization from power-up (cold start) assumes full supply voltage reached within 1 ms from power-up. short cycles exist prior to frequency stabilization. 1.5 ms z o ac output impedance average value during switching transition. used for determining series termination value. 25 ?
W215B preliminary document #: 38-07222 rev. *a* page 11 of 14 48-/24-mhz clock output (test load: r = 33 ? ; c = 22 pf) parameter description test condition/comments cpu = 100 mhz unit min. typ. max. m/n pll ratio 57/17 t r output rise edge rate 0.5 2 v/ns t f output fall edge rate 0.5 2 v/ns t d duty cycle measured on rising and falling edge at 1.5v 45 50 55 % f st frequency stabilization from power-up (cold start) assumes full supply voltage reached within 1 ms from power-up. short cycles exist prior to fre- quency stabilization. 3ms z o ac output impedance average value during switching transition. used for determining series termination value. 25 ? ordering information ordering code package name package type W215B x 48-pin tssop (6.1 mm)
W215B preliminary document #: 38-07222 rev. *a* page 12 of 14 layout example g +2.5v supply c1 c2 fb +3.3v supply c4 10 f fb c1 c2 0.005 f g g g g vddq2 vddq3 c3 g g 5 ? vddq3 c5 c6 48 47 46 45 44 43 42 41 40 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 39 g = via to gnd plane layer v =via to respective supply plane layer note: each supply plane or strip should have a ferrite bead and capacitors c1 & c3 = 10 ? 22 f c2 & c4 = 0.005 f fb = dale ilb1206 - 300 (300 ? @ 100 mhz) c5 = 47 f c6 = 0.1 f g v g v g v g v g v core vddq3 g v g v W215B g g g g g g g g g g g g g g g g g g 0.005 f 10 f
W215B preliminary document #: 38-07222 rev. *a* page 13 of 14 ? cypress semiconductor corporation, 2001. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do i ng so indemnifies cypress semiconductor against all charges. package diagram 48-pin small shrink outline package (tssop, 6.1 mm)
W215B preliminary document #: 38-07222 rev. *a* page 14 of 14 document title: W215B notebook pc system frequency generator for k6 processors document number: 38-07222 rev. ecn no. issue date orig. of change description of change ** 110487 10/21/01 szv change from spec number: 38-00886 to 38-07222 *a 122839 12/15/02 rbi added power-up requirements to maximum ratings information.

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